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Format 記事・論文

バンク型多ポートメモリによる並列プロセッサ用キャッシュメモリの設計

上口 光,朱 兆旻,平川 泰 他

details

Title バンク型多ポートメモリによる並列プロセッサ用キャッシュメモリの設計
Author 上口 光
Author 朱 兆旻
Author 平川 泰 他
Place of Publication (Country Code) JP
Year of Publication(W3CDTF) 2005-04-15
Subject Heading(Keyword) 多バンク
Subject Heading(Keyword) 統合キャッシュ
Subject Heading(Keyword) スーパスカラプロセッサ
Subject Heading(Keyword) マイクロプロセッサ
Subject Heading(Keyword) multi-port memory
Subject Heading(Keyword) multi-bank
Subject Heading(Keyword) cache
Subject Heading(Keyword) unified cache
Subject Heading(Keyword) superscalar
Subject Heading(Keyword) microprocessor
NDLC ZN33
Target Audience 一般
Material Type 記事・論文
is part of (URI Form) https://iss.ndl.go.jp/books/R100000002-I000000050569-00
is part of (ISSN Form) 09135685
is part of (ISSN-L Form) 09135685
Magazine-which-carries-the-article name 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報
Printing volume 105
Printing number 2
Printing page 25~30
Language(ISO639-2 Form) jpn : 日本語

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