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デジタル記事
インターネットで読める全国の図書館
- 件名Leakage power power reduction cache memory process variation
- 一般注記High Performance Embedded Architectures a...
- 関連情報Lecture Notes in Computer Science || 4917 || p224-239 http://www.slrc.kyus...
デジタル記事
インターネットで読める全国の図書館
- 要約等We observe that the same SRAM cell leaks dif......erently, under within-die process variations, when storing 0 and 1; t......ence can be up to 3 orders of magnitude (ave......g 57%) at 60mv variation of threshold volt......e (Vth). Thus, leakage can be reduced if most often the values with less leakage are stored in the cache SRAM cells. We show applicability of this proposal ......timization and software-level techniques for reducing instruction cache leakage: we (i) reorde......c-blocks so as to match up the i......ss-leaky state of their corresponding cache cells, (ii) st......tialize unused cache-lines to their corresponding ...
- 件名Leakage power power reduction cache memory process variation
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