検索結果 5 件
デジタル記事
インターネットで読める全国の図書館
- 件名test time CBET TAM external pins
- 関連情報Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design || || p683-688 http:.......csce.kyushu-u.ac.jp/SOC/index_j.html
デジタル記事
インターネットで読める全国の図書館
- 要約等External pins for test are precious hardware resources because this number......tricted. Cores are tested via test access mechanisms (TAMs) such as a test bus architecture. When cores are tested via test buses which have constant bit widths, test stimuli and test responses for a particular core have to be transported over these test buses. The cor......dths for input and output than test buses, and hence, for some part of the test, the TAMs are idle; this is a wasteful usage of the TAMs. In this paper, an optimization method of test accesses with a combined BIST and external test (CBET) scheme is proposed for eliminating t...
- 件名test time CBET TAM external pins
デジタル記事
インターネットで読める全国の図書館
- 要約等External pins for test are precious hardware resources because the number of them are strongly res......cted. In this paper, an optimization method of test accesses with a combined BIST and external test (CBET) scheme is proposed. The method can minimizes test application time and eliminate the wasteful usage of external pins considering the trade-off between test application time and the number of external pins. Our ideas consist of two parts. One is to ......ptimum groups each of which consists of cores to simultaneously share mechanisms for external test. The other is ......e the optimum bandwidth of external input and ...
- 件名Test Application Time BIST External Test CBET Test Scheduling Test Bus
- 著者標目Sugihara Makoto Yasuura Hiroto
デジタル記事
インターネットで読める全国の図書館
- 件名Test Application Time BIST External Test CBET Test Scheduling Test Bus
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