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デジタル記事
2008-10-15VLSI-SoC2008p.543-546
インターネットで読める全国の図書館
  • 要約等...design is becoming much difficult. The increase in parameter vari......rge design margins. However since the worst-ca......the design margin is often overe......imated. To eliminate the excessive design margin, designers sho......t case. We are investigating canary logic ...... logic can eliminate the excessive design margin by combined with Dynamic Voltage Scaling (DVS) system. A naive combination of the canary and the DVS suffers serious performance loss due to useless voltage scaling. In this paper, we......show where the performance loss comes from and......y logic to eliminate the excessive design margin without performance loss. VLS...
デジタル記事
国武, 勇次, 佐藤, 寿倫, 安浦, 寛人2008-10-15VLSI-SoC2008p.543-546
インターネットで読める全国の図書館
  • 関連情報VLSI-SoC || 2008 || p543-546 http:......kyushu-u.ac.jp/index-j.html http://vlsi.ee.duth...

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