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デジタル記事
インターネットで読める全国の図書館
- 要約等Share of leakage in cache memories is in......stored bits in instruction caches are zero, and hence, asymmetric SRAM cells which dissipate less leakage when storing 0......ctively reduce leakage with negligibl....... We show that by carefully choosing register operands of instructions, it is possib......ber of 0 bits, and hence, increase leakage savings in instruction cache. This compiler......ormed off-line and introduces abs......ince processor registers are all the s......improvement in leakage. Great Lakes S......4-6, 2008 : Orlando, Florida
- 標準番号（その他）https://hdl.handle.net/2324/10198
- 件名... Static memory SRAM Cache memory Compilers Optimization...
デジタル記事
インターネットで読める全国の図書館
- 件名... Static memory SRAM Cache memory Compilers Optimization...
- 一般注記Great Lakes Symposium on VLSI (GLSVLSI) 2008 : May 4-6, 2008 : Orlando, Florida
- 関連情報Great Lakes Symposium on VLSI || 2008 http://www.c.csce.kyushu...
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