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デジタル記事
佐藤, 寿倫, 千代延, 昭宏, 城, 和貴International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems2006-019th International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systemsp.21-28
インターネットで読める全国の図書館
デジタル記事
2006-019th International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systemsp.21-28
インターネットで読める全国の図書館
  • 要約等...research topic for modern microprocessors. We have been ......e resources. Unfortunately, our p......fers severe performance penalty. ......n in effective instruction issue queue (ISQ) ca......ure, redundant instructions occupy the IS......temporary microprocessors use a dedicate...... reduce the performance penalty, ...... ROBbased microprocessors. We reduce the......23.9% to 18.3% for integer and fl......Keywords: microprocessors, soft errors, ......rs, dependable processors, fault tolerance
  • 出版者(掲載誌)...e Architecture for Future Generation High Performance Processors and Systems

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