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Dynamically Variable Line-Size Cache Architecture for Merged DRAM/Logic LSIs

Dynamically Variable Line-Size Cache Architecture for Merged DRAM/Logic LSIs
デジタル記事
2000-05-25IEICE transactions on information and systemsE83-D 5p.1048-1057
インターネットで読める全国の図書館
  • 要約等This paper proposes a novel cache architecture suitable for merged DRAM/logic LSIs, which is called "dynamically variable line-size cache(D-VLS cache)." The D-VLS cache can optimize its line-size according to t......improve the performance by exploi......y bandwidth on merged DRAM/logic LSIs appropriately.......t-mapped D-VLS cache is about 20% c...... direct-mapped cache with fixed 32-......lines. This performance improveme...... direct-mapped cache.
  • 件名cache variable line-size merged DRAM/logic LSIs high bandwidth

Dynamically Variable Line-Size Cache Architecture for Merged DRAM/Logic LSIs

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デジタル記事
井上, 弘士, 甲斐, 康司, 村上, 和彰電子情報通信学会2000-05-25IEICE transactions on information and systemsE83-D 5p.1048-1057
インターネットで読める全国の図書館
  • 件名cache variable line-size merged DRAM/logic LSIs high bandwidth
  • 関連情報IEICE transactions on information and systems || E83-D(5)...

Dynamically Variable Line-Size Cache Architecture for Merged DRAM/Logic LSIs

Dynamically Variable Line-Size Cache Architecture for Merged DRAM/Logic LSIs
記事
2000IEICE Trans. Electronics83 5p.1048-1057
全国の図書館

Dynamically variable line-size cache architecture for merged DRAM/logic LSIs

Dynamically variable line-size cache architecture for merged DRAM/logic LSIs
記事
2000IEICE Trans. Inf. & Syst.83 5p.1048-1057
全国の図書館

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