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- 要約等This paper proposes an architecture for low-power direct-mapped instruction caches, called “history-based tag-comparison (HBTC) cache”. The HBTC cache attempts to detect and omit unnecessary tag checks at run time. Execution footprints are recorded in an extended BTB (Branch Target Buffer), and are used to know the cache residence of target instructions before starting cache access. In our simulation, it is observed that our approach can reduce the total count of tag checks by 90 ......ing in 15 % of cache-energy reducti......n, with less than 0.5 % performance degradation.
- 標準番号（その他）https://hdl.handle.net/2324/3605
- 件名cache low power tag check dynamic optimization BTB
デジタル記事
インターネットで読める全国の図書館
- 件名cache low power tag check dynamic optimization BTB
- 関連情報...kshop on Power Aware Computer Systems (PACS02)|| || p15-22 http://.......csce.kyushu-u.ac.jp/SOC/index_j.html
- 著者標目井上, 弘士 Moshnyaga, Vasily G. 村上, 和彰
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