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An On-chip Memory-Path Architecture on Merged DRAM/Logic LSIs for High-Performance/Log-Energy Consumption

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デジタル記事
井上, 弘士, 甲斐, 康司, 村上, 和彰2000-04Proceedings of International Symposium on Low-Power and High-Speed Chips (COOL Chips III)p.283-283
インターネットで読める全国の図書館
  • 件名merged DRAM/logic LSI DRAM/ロジック混載LSI
  • 一般注記International Symposium on Low-Power and High-Speed Chips (COOL Chips...
  • 関連情報Proceedings of International Symposium on Low-Power and High-Speed Ch......OOL Chips III) || || p283 http://www.c.csce.kyushu...

An On-chip Memory-Path Architecture on Merged DRAM/Logic LSIs for High-Performance/Log-Energy Consumption

An On-chip Memory-Path Architecture on Merged DRAM/Logic LSIs for High-Performance/Log-Energy Consumption
デジタル記事
2000-04Proceedings of International Symposium on Low-Power and High-Speed Chips (COOL Chips III)p.283-283
インターネットで読める全国の図書館
  • 要約等International Symposium on Low-Power and High-Speed Chips (COOL Chips...
  • 標準番号（その他）https://hdl.handle.net/2324/7346
  • 件名merged DRAM/logic LSI DRAM/ロジック混載LSI

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