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- 要約等...nologies will make the worst-case design impos......e, since they can not provide design margins that it requires. Research directions should go to typical-case design methodo......here designers are focusing on typical cases rather than worrying about very rare worst cases. In this paper, canary logic is proposed as a promising technique that enables the typical-case design. It is easier to design than the previously proposed Razor logic by eliminating delayed clock. Estimates based on gate-level simulations show that the canary logic achieves average power reduct...... exploiting dynamic variations in circuit delay. 8th...
- 出版者（掲載誌）International Symposium on Computer Quality Electronic Design
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- 参照Dual Edge Triggered Flip-Flops for Noise Blocking and Application to Signal Delay Detection 超低電......ブスレッショルド回路設計技術 A Statistical Maximum Algorithm for Gaussian Mixture Model......ering the Cumulative Distributi......nction Curve Real Circuit Delay Measurement Method by Variable Frequency Operation with On-Ch......solution Oscillator Multi-scenario high-level synthesis for dynamic delay variation and its evaluation on FPGA platforms An Effective Sus......ror Prediction Circuit Insertion Algorithm Minimizing Area Overhead A Multi-Scenario High-Level Synthesis Algorithm for Variation-Tolerant Floorplan-Driven Design Trade-Off Anal...
デジタル記事
インターネットで読める全国の図書館
- 一般注記8th International Symposium on Quality Electronic Design : March 26-28, 2007, San Jose, CA, USA
- 関連情報Proc. of 8th International Symposium on Quality Electronic Design || || p539-545 http:....../www.isqed.org/Archive/ISQED'07.......csce.kyushu-u.ac.jp/SOC/index.html
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