「A Low Power I-Cache Design with Tag-Comparison Reuse」のOpenURLのAPI検索結果 | NDLサーチ

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井上, 弘士, 田中, 秀和, モシニャガ, ワシリー, 村上, 和彰IEEE2004-11Proc. of the The International Symposium on System-On-Chip (SOC04)p.61-67

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関連情報Proc. of the The International Symposium on ......n-Chip (SOC04) || || p61-67 http://.......csce.kyushu-u.ac.jp/SOC/index_j.html

デジタル記事

2004-11Proc. of the The International Symposium on System-On-Chip (SOC04)p.61-67

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要約等This paper reports design and evaluation results of a low-energy I-cache architecture, called history-based tagcomparison (HBTC) cache. The HBTC cache attempts to re-use tag-comparison results to detect and eliminate unnecessary memory-array activations. We have performed cycle accurate simulations, and have designed an SRAM core based on a 0.18 $ mu m $ ......OS technology. As a result, it has been observed that the HBTC approach can achieve 60% of e......rgy reduction, with only 0.3% performance degradation, compared to a conventional cache. Furthermore, we have also evaluated the potential of the HBTC cache by combining with other lo...

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2004Proceedings of the International Symposium on System-On-Chip (SOC04)p.148-153

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記事

2004Proc.of the The International Symposium on System-On-Chip(SOOO4)p.61-67

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