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デジタル記事
インターネットで読める全国の図書館
- 要約等...gh exploiting fault-free sections of defective chips is a well-known technique [1][2]. The idea is to partition the circuitry of a chip in a way that faultfree sections can function independently. Many fault tolerant techniques for improving the yield of processors with a cache memory have been propose......][5]. In this paper, we propose a defect-aware code placement technique which offsets the performance degradation of a processor with a defective cache memory. To the best of our knowledge, this is the first compiler-based technique which offsets the performance degradation due to cache defects. Ex......iments demonstrate that the technique can comp...
- 著者標目Ishihara Tohru Fallah Farzan
- 出版者（掲載誌）International Conference on Computer Aided Design
デジタル記事
インターネットで読める全国の図書館
- 著者標目石原, 亨 Fallah, Farzan
記事
全国の図書館
- 著者標目ISHIHARA T.
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